VHDL实现快速傅立叶变换

it will count the bit

buffer for in/out data.

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules

vhdl source code for 8 bit datapath logic

vhdl,无进位同步计数器，完成6进制加，输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences

HDB3 encoder and decoder(HDB3 decoer)

基于VHDL的I2C程序0005,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0005, a very good paper and procedures, we quickly under ah

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  SHA-1加密算法的IP核，内涵文档，仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)