VHDL实现快速傅立叶变换

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar

基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)

dos下的svga图形库，包括读bmp位图，打点划线等(svga graphics library under dos)

自动白平衡的verilog实现 通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )

本压缩包，包换一个用verilog语言实现的huffman编码源程序，同时给出了众多论文和基础知识的文档资料，一应俱全。(The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.)

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)

设计一4位比较器,画出门级电路图,用verilog语言完成设计。 (Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )

使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)

采用VHDL编写的频率计，模块划分清晰易懂，基本原理为检测一个闸门脉冲周期内的信号次数，采用四段数码管显示

PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!