xapp from xilinx very hard to find and very usefull application note from the gr...

CAN VHDL Code. Behavioral implementation of CAN bus interface.

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)

Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)

SED1330/1335/1336/E1330液晶显示控制器及51汇编源程序.液晶显示程序,显示图形及汉字.-SED1330/1335/1336/E1330 LCD controller and the source of 51 Series procedures. LCD procedures, and show pictures of Chinese characters.

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

用verilog编程的TCON模块（时序控制器）的程序(Verilog programming module with TCON (timing controller) program)

硬件描述语言,verilog HDL,实现了解码器的设计-hardware description language, verilog HDL, the decoding of Design

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

最近交互式电源技术，软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)