xapp from xilinx very hard to find and very usefull application note from the gr...

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

本代码为简单AXI接口控制模块，具备数据的读写等传输功能，对总线传输学习者来说是很好的学习资料，可在此代码基础上进行更复杂功能接口的模块的开发。

JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)

利用FPGA实现对外设按键的控制，例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)

复旦cpu COS

世界时钟，最简单的vhdl的fpga设计，是vhdl语言的入门级，jigon供参考娱乐

ahb to apb master and slave

Xilinx PicoBlaze application developed in ISE10.1.3.