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一个简单的曼彻斯特编码器,将串行数据转换为曼彻斯特编码数据。
A simple Manchester Encoder to convert serial data to Manchester encoded data.
- 2022-06-20 14:27:09下载
- 积分:1
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802.1as
802.1as gptp标准包解析verilog模块。用于实现EAVB协议的重要部分。(802.1as gptp verilog module, part of EAVB procotol)
- 2017-02-07 15:16:39下载
- 积分:1
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可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的...
可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的-Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon
- 2022-07-09 12:07:56下载
- 积分:1
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use of the VHDL language ALTERA company's board up3 have vga signal containi...
使用vhdl语言在altera公司的up3板上产生vga信号,里面有详细的解析和说明,是一个很好的教程。和上一个文件razzle差不多,但是产生的效果不一样。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.
- 2022-01-31 21:08:09下载
- 积分:1
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design through verilog hdl
design through verilog hdl
- 2023-04-07 06:25:04下载
- 积分:1
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data_rom
正弦信号发生器,用VHDL来完成,抗干扰能力较强,(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)
- 2009-07-15 22:44:02下载
- 积分:1
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Xilinx PicoBlaze的解释
Xilinx picoBlaze explained
- 2022-01-26 03:15:36下载
- 积分:1
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CD1_MT9V034_RAW_TRANS
基于FPGA的UDP网络图像传输实验,FPGA完成了MT9V034的RAW图像采集缓存,NIOS完成了图像的UDP封包,DM9000芯片完成了MAC和PHY的功能。(Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM9000 chip MAC and PHY completed the function.)
- 2016-07-13 10:11:46下载
- 积分:1
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FPGA based implementation of a SDR
FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
- 2022-12-18 09:05:03下载
- 积分:1
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VHDL 编写的RAM例子
VHDL 编写的RAM例子-RAM prepared VHDL example
- 2023-03-23 05:20:03下载
- 积分:1