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VHDL 0~
程序用VHDL实现:
利用一秒定时测量频率
并且显示,范围0~-VHDL 0~
- 2022-05-15 03:55:50下载
- 积分:1
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VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
- 2022-02-11 16:15:23下载
- 积分:1
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fre
本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)
- 2015-08-12 08:39:32下载
- 积分:1
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jpeg_fpga
基于FPGA的JPEG解码,对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)
- 2014-02-24 09:19:22下载
- 积分:1
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程序
说明: 传感器是一种检测装置,能感受到被测量的信息,并能将感受到的信息,按一定规律变换成为电信号或其他所需形式的信息输出,以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)
- 2020-06-18 22:00:01下载
- 积分:1
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DSP28335_SPI_FPGA_RECE
DSP28335与FPGA通过spi通信,此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)
- 2020-12-09 13:39:19下载
- 积分:1
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本文件是用CPLD(EPM7064)驱动线阵CCD(ILX509),其中包括原理图和程序...
本文件是用CPLD(EPM7064)驱动线阵CCD(ILX509),其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures
- 2022-02-12 02:58:13下载
- 积分:1
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pps_ketiao_rb2
说明: FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
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EDA
EDA技术及其应用《序列信号发生器的设计》,包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)
- 2012-10-29 18:30:40下载
- 积分:1
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BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分:1