在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配...

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)

FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO

四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.

VHDL语言实现PWM信号，非常方便的使用-VHDL language realize PWM signal, very convenient to use

出租车vhdl程序，并带有testbench仿真程序，通过开始按键复位，然后根据行使信号进行公里计数，起步价3公里8元钱，超过3公里一公里1元钱(Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometers one kilometer dollar.)

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.

altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical