在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配...

数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)

0到255任意整数半整数分频Verilog HDL.rar-0-255 arbitrary integer half-integer frequency division Verilog HDL.rar

用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete

Qutuas II v7.1的key_gen 对sp1无效 这就是个v7.1 sp1的key_gen -Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen

基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!

基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter

pci协议主模块开发实用代码， 适合初级学习者使用 很不错(pci agreement to develop practical code, very good for junior learners)

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

this come from alter ,you can look and find it on line.

VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins