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TW2867_ADV7171
FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)
- 2021-03-19 15:19:19下载
- 积分:1
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是使用VHDL语言编写的基于FPGA的uart的源代码!
是使用VHDL语言编写的基于FPGA的uart的源代码!-VHDL language is to use FPGA-based uart source code!
- 2022-07-10 13:34:40下载
- 积分:1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分:1
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SinGen
使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)
- 2015-04-24 16:40:21下载
- 积分:1
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FFT
verilog xilinx IP实现FFT仿真(Verilog xilinx IP implementation FFT simulation)
- 2017-03-14 00:15:29下载
- 积分:1
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RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar...
RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar-RSA password chip FPGA realization of [1]. Part1.rarRSA password chip FPGA realization of [1]. Part1.rar
- 2022-08-13 06:54:28下载
- 积分:1
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shiyan5
应用布莱克曼窗实现FIR滤波器,并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分:1
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1553B总线接口技术研究及FPGA实现
说明: 基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)
- 2019-04-18 11:02:52下载
- 积分:1
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DecimationFilterDesignforDDCandImplementingItwithF
本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB
滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)
- 2008-04-14 11:02:00下载
- 积分:1
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VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...
VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
- 2022-05-08 02:59:08下载
- 积分:1