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Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计,
内有全套源码以及图片,内容详尽,绝对真实可靠!(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分:1
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cycloneII ep2c5 ep2c8
cycloneII ep2c5 ep2c8
- 2022-06-26 08:54:36下载
- 积分:1
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基于verilog的1588V2协议的fpga实现
基于verilog的1588V2协议的fpga实现,目前项目通用代码,供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)
- 2021-04-26 10:58:46下载
- 积分:1
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tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分:1
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USB245I based FPGA VHDL of the driver, should useful
USB245I的基于FPGA的VHDL语言的驱动程序,应该有用-USB245I based FPGA VHDL of the driver, should useful
- 2022-08-09 23:10:50下载
- 积分:1
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华勒斯树结构的8位修正展位乘数
应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码,华勒斯树和超前进位addder关键技术超大规模集成电路设计,通信和DSP的应用,芯片设计,VHDL,Verilog程序,加法器和乘法器
- 2022-02-04 19:57:10下载
- 积分:1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分:1
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vhdl 加法器 vhdl 加法器
vhdl 加法器
vhdl 加法器 vhdl 加法器
vhdl 加法器-vhdl adder vhdl adder vhdl adder
- 2022-09-01 23:25:03下载
- 积分:1
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vga_core
Code VHDL for control VGA
FPGA: Xilinx, Altera
- 2012-09-09 10:54:28下载
- 积分:1
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Applicable to FPGA
适用于FPGA的SOPC方面的元器件添加,如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2023-06-04 02:30:03下载
- 积分:1