verilog写的数字频率计的显示模块,可以

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

PID算法控制点击速度，PWM脉宽调制方法(PID algorithm to control the motor Speed)

LDPC encoding code in 1/2code rate for DVB-T2

这是一本介绍FPGA设计过程中关键问题的资料书,对参加面试或工程设计有一定帮助-This is an FPGA design process, introduce the key issues of information written on the interview or take part in engineering design has a certain extent, help

there are exemple in the vhdl

FSK信号发生器，基于VHDL语言，好用的！-FSK signal generator, based on the VHDL language, useful!

8倍抽取的DDC模块。verilog写的，调试通过(failed to translate)

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

8051 1Khz sine wave generator. make use of DAC0808 and timer 0 interrupt. Also single led is blinked continuously.

数字电路的设计。以软件方式实现硬件电路，功能强大，开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy. )