用于fpga学习，共同分享学习经验和交流学习心得

This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6

说明：  ADC Reference code!Clock 100kHz

LDPC COded OFDM System

说明：  Matlab to hdl code for Least_square testbench

crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)

基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a