ALU vhdl

程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM

基于FPGA的任意波形信号发生器,可实现频率、幅度、相位的调节，输出方波、正弦波、锯齿波(Arbitrary waveform generator based on FPGA)

Altera 基础篇公司书籍源码-Altera Corporation based on chapter books-source

emmc控制芯片CMD命令线主机接口模块,(emmc control chip CMD command line host interface module)

三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words

国外经典verilog代码，很适合初学者，其中的有些概念对老手也可以考虑下-Foreign classic Verilog code, it is suitable for beginners, of which some of the concept of a veteran may also want to consider under the

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

ram 64KB designed by haneesh in verilog