ALU vhdl

Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic

给出了脉冲多普勒雷达相参积累的vhdl程序，可作为参考。主要的是设计思想，看之前得掌握相参积累的原理

QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the

FSM_test for textbanch in vhdl-FSM_test

利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)

关于I2C总线协议的verilog代码，里面包括了3个verilog代码(I2C bus protocol verilog code, which includes three verilog code)