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这是一个vhdl代码的进位选择加法器及其工作100%。

verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table

从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式(bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal)

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)

VGA interface using Spartan3E board from DIGILENT.Labview .vi

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!-16 CUPIP nuclear, full of good things to run, can be directly used to use!

说明：  document qpsk vhdl code

本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!

relative cpu design implementation

应用背景VHDL  ；CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL  ；CPU设计...................................................................................................................................