err

海德汉绝对式编码器代码，VHDL语言编写(Heidenhain absolute encoder code, VHDL language)

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT STATIC RAM)

This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.

基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of

说明：  XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)

青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err

说明：  使用VHDL实现的LED-80分组密钥，相对于其它密钥具有硬件实现面积更小的特点(vhd code of a lightweight block cipher LED-80)

基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source