FPGA

QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)

用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.

设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend

Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize

自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

this is a verilog code of true random number generator using butterfly puf