avaloncsequencer

FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures

Modelsim 5.6 se 简易使用教程 -Modelsim 5.6 se easy to use tutorial

FFT处理器的FPGA设计方法，适合做信号处理的技术人员参考，用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

HARIS角点检测Harris角点检测HARRIS CORENR探测器

本程序实现任意占空比产生，已经在easyfpga030综合过-This procedure generated to achieve an arbitrary duty cycle

verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language

展位的乘法算法 is a 乘法算法两者相乘得两个签名二进制 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode