FPGA设计的I2C总线控制器的MASTER端的程序

xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1. 乘法算法采用原码移位乘法，即对两个操作数进行逐位的移位相加，迭代4次后输出结果。具体算法： 1. 被乘数和乘数的高位补0，扩展成8位。 2. 乘法依次向右移位，并检查其最低位，如果为1，则将被乘数和部分和相加，然后将被乘数向左移位；如果为0，则仅仅将被乘数向左移位。移位时，被乘数的低端和乘数的高端均移入0. 3. 当乘数变成全0后，乘法结束。 -err

Altera board Mp3 project

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.

说明：  这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)

文件中包含BFSK、DPSK、BPSK、QPSK等等数字调制程序。(File contains the BFSK, DPSK, BPSK, QPSK, and so on digital modulation process.)

说明：  基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)