HARRIS 角点检测算法

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

说明：  使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

十进制精确计数，经典写法，便于学习与参考，供大家分享-Decimal precision counts, classic written, easy learning and reference for all to share

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.-Used VerilogHDL to make a frequency builder.

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)