HARRIS 角点检测算法

这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine

由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

vhdl语言编程入门实例100个，部分附有仿真波形图，和一些基本的讲解-vhdl examples

RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)

开关数据加载到寄存器并显示的设计与实现.3． 设计一个可以把4个开关的内容存储到一个4位寄存器的电路，并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse， 用btn[0]作为输入；8位寄存器模块，用btn[1]作为加载信号；7段显示管上的显示模块x7segbc；分频模块clkdiv，用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)

本程序主要是实现xinlinx fpga与dsp之间的双工通信(This program is to achieve duplex communication between xilinx fpga and dsp)

使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)

Paint for SPARTAN 3E

说明：  八通道ad采集，用于和fpga的联调测试，需要注意ADS1278的模式类型(Eight channel AD acquisition)