布斯算法

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

说明：  实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

基于vhdl的pid控制器设计，可以用quartus等软件实现。数字控制系统pid设计源代码。(Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co)

一个AD9764的基于FPGA的驱动，希望对有需要的朋友有所帮助(An AD9764 FPGA-based drive, we want to help a friend in need)

LVDS并行数据传输，来自XILINX官网(LVDS Parallel Data Transfer)

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

步进电机定位控制系统，VHDL程序，里面有注释(Stepper motor position control system, VHDL program, there are comments)

verilog code for bus controller