布斯算法

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

基于软输出固定复杂度球形译码的高效迭代检测算法，最新的球形译码论文(Iterative detection algorithm based on a fixed complexity soft-output sphere decoding efficiency, sphere decoding papers)

this is a verilog code of true random number generator using butterfly puf

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)