布斯算法

说明：  stepper motor module on spartan 6 and 24MHz clock fequency

一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference

VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言(verilog language manuals, and the other enjoying VHDL hardware description language 1)

该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

计算机中每一条机器指令的执行，都离不开程序计数器的正确执行，本程序实现程序计数器。(Computer implementation of each machine instruction, are inseparable from the correct implementation of the program counter, this program achieve the program counter.)

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)

说明：  关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典(Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure)

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

说明：  Matlab - to hdl code for square root