本程序实现任意占空比产生，已经在easyfpga030综合过

这是led流水灯的vhdl描述，很好的啊-led s hdl describe

说明：  verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)

该代码实现了IIC对24C02的读写，写采用页写的方式，读采用随机的方式。(This code implements the IIC on 24C02 read and write, write, write using the page mode, read random way.)

HDL example source code 1/5 dff_as

说明：  实现UDP的网络传输，在PC建立UDP的服务器，向fpga的ip：192.168.0.25发送数据，实现回环通讯。(The network transmission of UDP is realized. UDP server is set up in PC, and the data is sent to IP: 192.168.0.25 of FPGA to realize loop communication.)

可以产生ASK FSK PSK 等调制信号。非常好用已经实现了所有功能。在硬件测试通过了(Can generate ASK FSK PSK modulated signals and so on. Is very easy to use all the features has been achieved. On the hardware test of the)

说明：  学习fpga的工具signaltap软件使用说明书，好工具(Learn the instruction manual of signaltap software, a good tool)

模数转换的一个工程---包括vhdl源程序和编译后产生的相关文件-Analog-digital conversion of a project- including VHDL source code and compile the relevant documents after