M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.

Toplevel VHDL Structural model of a system containing 8051 -Toplevel VHDL Structural model of a system containing 8051

FPGA设计的四种常用思想与技巧分享:串并转换设计技巧、流水线设计思想……(FPGA design of four common ideas and techniques)

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

Free 8051 core upload

SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps

用verilog编写的can总线控制器，包括设计参考历程和仿真程序，以及开发文档！(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)

各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8(CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8 )