FFT的VHDL源代码

XILINX中LWIP协议例子应用指南，有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)

纠错和单故障检测代码使用正交拉丁方是用VHDL语言写的。

本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!

This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

使用VHDL键盘扫描程序，可以稍微修改一下使用

该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.

build a tv box on fpga cyclone 2

说明：  写出13个简单的Verilog demon，适合初学者观摩学习。配合实验报告，食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)

电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)