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Arbitrary odd
任意奇数分频,只要修改N即可实现 可验证-Arbitrary odd-numbered sub-frequency, as long as the modified N can realize verifiable
- 2022-03-19 01:50:16下载
- 积分:1
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LightControl
说明: 经典的雷鸟车灯控制电路设计,各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)
- 2011-03-05 09:49:32下载
- 积分:1
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Synchronous Resets Asynchronous Resets I am so confused! How will I ever know wh...
Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper
- 2022-03-02 03:52:16下载
- 积分:1
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Verilog
用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)
- 2021-03-25 15:49:14下载
- 积分:1
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taxivalue
我用FPGA来实现,这是一个出租车计价器,用来计算里程,我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)
- 2020-07-12 19:08:52下载
- 积分:1
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FPGA实现 DDS_讲的非常详细,师兄的一片论文
FPGA实现 DDS_讲的非常详细,师兄的一片论文-FPGA realize DDS_ talked about in great detail, of a senior thesis
- 2023-03-01 11:00:04下载
- 积分:1
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实用的程序代码,希望对大家有用,已经调试通过
实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
- 2022-06-03 06:28:25下载
- 积分:1
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chenxu
电子时钟,可以显示四位,两位显示分钟,两位显示秒,可以用按键控制清零,以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
- 2017-04-22 21:29:14下载
- 积分:1
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task_function
自己编写的一个verilog HDL小程序,实现基本的task调用function的功能,对初学者有用。在xilinx的ISE仿真调试通过(I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through)
- 2008-06-26 21:21:23下载
- 积分:1
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filter-design
MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)
- 2020-12-02 20:39:26下载
- 积分:1