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AN66806
提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)
- 2013-08-13 14:42:55下载
- 积分:1
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I2C verilog 源代码 非常好的代码,大家可以
I2C verilog 源代码 非常好的代码,大家可以-I2C verilog source code for a very good code, we can
- 2022-03-14 16:49:14下载
- 积分:1
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OFDM
:采用FPGA来实现一个基于OFDM技术的通信系统中的基带数据处理部分,即调制解调器。其中发射部分的调制器包括:信道编码(Reed-Solomon编码),交织,星座映射,FFT和插入循环前缀等模块。我另外制作了相应的解调器,可以实现上述功能的逆变换。(: Using FPGA to implement a technology-based OFDM communication systems in base-band data processing part of the modem. One part of the modulator launch include: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and cyclic prefix insertion modules. I also produced a corresponding demodulator can achieve the above-mentioned inverse transform function.)
- 2009-04-16 12:28:17下载
- 积分:1
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基于FPGA实现数控机床高速运动的DDA设计
本文利用FPGA 可以弥补硬件插补器的不足,是执行速度提高,且可与运动控制部分很好的集成,制成运动控制器,实现高速运动控制
- 2022-03-10 10:19:20下载
- 积分:1
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DDS
说明: 使用Verilog,以Quartus II 为平台,编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)
- 2020-11-26 17:12:26下载
- 积分:1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分:1
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步进电机控制程序,用vhdl实现。可实现电机的正反转控制
步进电机控制程序,用vhdl实现。可实现电机的正反转控制-Stepper motor control program, using vhdl implementation. Positive inversion of motor control can be realized
- 2022-03-03 18:23:56下载
- 积分:1
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SystemVerilog_For_Design_Springer_2nd_Ed_2006
SystemVerilog For Design (Springer-2nd_Ed-2006)
- 2009-10-08 02:57:28下载
- 积分:1
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ComChange-12061629
说明: 并行读写14路串口数据,数据被写入FIFO,在收到读写信号后,SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分:1
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3-8
3-8译码器,可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分:1