简易cpu的设计

本文详细介绍了我们的电气工程项目；

用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)

ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

本例源代码文件由用户按照书中的操作步骤自己生成，“Example-2-1Project_Navigator_Demo源代码”目录下为源代码的参考文件。“Example-2-1Project_Navigator_Democounter”目录下为完整的工程，包括源代码文件、综合与实现的结果文件、ISE工程文件等，可以使用ISE工程管理器打开工程，供读者参考(In this case the source code files by the user in accordance with the steps the book itself is generated, "Example-2-1 Project_Navigator_Demo source" directory as the source code reference document. "Example-2-1 Project_Navigator_Demo counter" directory for a complete project, including source code files, integrated with the realization of the outcome document, ISE project file, etc. You can use ISE Project Manager, open the project for the reader is referred to)

xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)

用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code

vhdl code for fir filter

使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM