利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能...

this the for a equiripple filter-this is the for a equiripple filter

一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench

改写四号中断的 自己编的，，，，，，求过啊！！！一个很简单的小程序(Rewrite the fourth interruption of their series,,,,,, begged ah! ! ! A very simple little program)

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

UART 源码 (lattice version)-UART source (lattice version)

一段很好地讲述PWM的VHDL硬件代码，可以在不同SOPC上运行实现

第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer

彩色空间转换，RGB和YUV互转的matlab源码(RGB converting to YUV, YUV converting to RGB, Matlab source code)

32位二进制除法器2

- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)