Quartus flv configuration and commissioning of the

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

180nm数字教学库，内含各种标准数字单元(180nm digital lib for education, including standard cells)

VGA字符显示VHDL程序 可以直接用于工程的设计与开发-VGA display characters can be directly used for VHDL design and development

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

VHDL2verilog的程序，相信对大家很有帮助-VHDL2verilog procedures, I believe very helpful to everyone

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)