FSM_test for textbanch in vhdl

基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)

用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes

FPGA做机器人舵机控制系统，verilog(FPGA to do the robot servo control system, verilog)

脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench

LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device

fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code

说明：  一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)

说明：  SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)