fpga clock design, the information is better, for your reference, non

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。(Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module. )

DE2将连接到LCD布局上，为Terasic off技术公司附上系统代码

AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)

用fpga制作一个音乐播放器，此为浙江大学信电系fpga教程大实验成果。(Use fpga make a music player, this is the letter Electrical Zhejiang University fpga tutorial big experiment results.)

VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.

4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)

自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过(I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through)