fpga clock design, the information is better, for your reference, non

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)

通过神经网络实现的PID算法，整个工程文件，调试通过。(By PID algorithm neural networks, the entire project files, debugging through.)

8级cordic 算法verilog (8 cordic algorithm verilog)

Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)

一位LED显示的VHDL程序，挺简单的，买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone

fpga上实现的51内核，带有LCD试验，顺利试验成功很好用。(on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.)

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

最终FFT 64点使用定点。

时钟输入：在每个时钟的正沿或负沿对数据进行处理 联合开发网 - pudn.com