Verilog HDL编写的CPU模型，很经典，比较通用

有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

Led灯控制实验用例 目录文件结构： led_test ├─ main.c C语言主源文件 └─ led.c Led灯控制函数源文件(Led lamp control experiment directory file structure use case: led_test ├ ─ main.c C language source file owners └ ─ led.c Led lamp control function source file)

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的.-VHDL state machine design examples, good for the state machine to figure out would be very useful.

Material to learn how to use system verilog and how to write testbenches for verification.

relative cpu design implementation

四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

its the vhdl stuff for ddr sdram controller nice one easily understandable