Verilog HDL编写的CPU模型，很经典，比较通用

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

huffman transform in vhdl language

airthmatic & logic unit

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

基于DE2开发板的VGA显示模块，仅供大家参考-DE2 development board based on the VGA display module, for your reference

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

SPI的VHDL程序，经过quartus验证的，不错！-SPI of the VHDL program, after verification quartus, yes!

基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)

通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）(m sequence vhdl)