VHDL language used to achieve 8

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)

典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在project文件夹里面 3. 源文件和管脚分配在 tl文件夹里面 4. 下载文件在download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects project folder inside 3. the distribution of the source file and pin in rtl folder inside 4. download files in download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.

MD5 算法在Xilinx FPGA上的实现，希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)

verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

本设计可直接用作时钟计数器，同时有调时，定时功能。 Led[3:0]显示秒钟的变化情况。 func用作计时，调时，定时功能转换。 Ledarrive用于提示计时时间已到。 change可使秒钟在数码管显示。 plus键在调时计时时使时钟加一。 shift用于调时计时时分计时与时计时的调整转换。