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FPGA_homewrk4
设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述,给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)
- 2018-05-07 17:54:12下载
- 积分:1
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T8051
IT8051,增强版的T51,兼容DW8051核的多数端口,IO需要扩展后使用
- 2022-02-12 17:39:36下载
- 积分:1
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sd_ctrl
利用verilog实现对SD卡的控制,可以实现对SD卡的读写。(Verilog SD)
- 2020-12-27 21:49:03下载
- 积分:1
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Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
周立功Verilog HDL黄金参考指南,学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
- 2022-04-28 19:53:04下载
- 积分:1
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qpsk
QFSK的调制与解调,用C写的主程序,汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)
- 2020-07-01 19:20:02下载
- 积分:1
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c8
说明: QPSK 调制 与 解调的源代码 可综合 出波形(QPSK modulation and demodulation of the source code)
- 2011-03-04 00:17:17下载
- 积分:1
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stopwatch-based-on-VHDL
基于VHDL的电子秒表的设计,使用VHDL语言描述一个秒表电路,利用QuantusII软件进行源程序设计,编译,仿真,最后形成下载文件下载至装有FPGA芯片的实验箱,进行硬件测试,要求实现秒表功能。(Design of electronic stopwatch based on VHDL)
- 2013-11-27 15:42:41下载
- 积分:1
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SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器,寄存器中存放的是奇数帧的同步头,也就是110。
EVEN_9BHREG是一个8位的备份寄存器,寄存器中存放的是偶数帧的同步头,也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分:1
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数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分:1
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QMD
说明: 实现了QPSK的调制,使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)
- 2019-05-05 15:37:58下载
- 积分:1