VHDL分频程序

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)

System Verilog for design verification

32 bit RISC Processor with 3 stage pipeline

现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。-Kabuki现rough cleaning转Connaught distance RGB to Y CbCr cavity VHDL Daitou Tungsten measurements 。

由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)

Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)

基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。(8B10B encoder)

电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text Foreign electronic and communication textbooks)

完整的PIC16系列单片机verilog描述-A complete description of PIC16 series of microcontrollers verilog

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)