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youmui_v20
ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.
- 2017-09-01 20:51:26下载
- 积分:1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计,要求使用Verilog语言编写滤波器模块,通过编译和综合,并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分:1
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有例在VHDL
there are exemple in the vhdl
- 2022-11-14 07:15:02下载
- 积分:1
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cordic-algorithm
codic algorithm,which is used to calculate triangular functions
- 2014-12-25 16:44:36下载
- 积分:1
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4*4按键扫描电路
4*4按键扫描电路,用数码管显示0~F,基于VHDL语言设计,包括按键扫描,数码管扫描,数码管显示,按键消抖等代码
- 2022-01-25 15:08:35下载
- 积分:1
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Get-20-point
this program get 20 point from user and draw functions.
- 2014-01-09 03:25:06下载
- 积分:1
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分数时延FIR
说明: 分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)
- 2019-11-18 22:45:35下载
- 积分:1
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01_rtc_ds1302
说明: 实现基于黑金开发板的实时时钟功能,显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)
- 2021-01-11 14:40:12下载
- 积分:1
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222
说明: VHDL BISS,SSI,ENDAT2.2, ENCODER
- 2020-11-24 17:46:39下载
- 积分:1
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dot_product
实现矩阵相乘,即点积运算,为VERILOG语言。可以根据自己的需要改变维数,采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)
- 2015-01-27 10:52:52下载
- 积分:1