verilog实现的“并行输入、并行输出移位寄存器”

FPGA的存储器代码的VHDL,verilog描述及测试代码-FPGA memory code VHDL, verilog description and test code

关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

VHDL tutorial for beginning learner

freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog

使用Verilog完成DS1302的驱动，工程已经经过测试，可直接使用。(DS1302 using Verilog complete drive, the project has been tested and can be used directly.)

直接序列扩频通信（主要包括BPSK调制和BPSK解调以及PN码的产生）(Direct sequence spread spectrum communication (including BPSK BPSK modulation and demodulation, and the PN code generation))

一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

spwm dcac逆变 fpga与单片机一起作用(sdad)