verilog实现的“并行输入、并行输出移位寄存器”

测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)

ANALYSIS OF D-FLIPFLOPS

CPLD实用设计50例，非常经典的CPLD设计，包含50个实际的典型应用，涉及直流电机PWM驱动，编码等内容，有了这50例，举一反三，就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )

Disparity mapp code in VHDL

说明：  2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.

这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference

vhdl code fpga for lcd 2*16