8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4...

build synthesizer on a de2 dev fpga board

rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange

用NIOSII生成的VGA显示程序,可以在显示器上显示通讯内容

verilog lcd2864 适合初学者(verilog lcd2864 )

说明：  具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data

最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))

FPGA代码，Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc

基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)