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ddr3_mig8
fpga实现ddr数据收发测试,完整的工程,下载解压后,即可正确运行,已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
- 2018-01-18 21:05:12下载
- 积分:1
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clock for spartan 3 evaluatoin board
clock for spartan 3 evaluatoin board
- 2022-02-28 19:30:52下载
- 积分:1
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pc104接口的verilog代码,仅供参考
pc104接口的verilog代码,仅供参考-pc104 verilog interface code for reference purposes only
- 2022-12-27 10:00:03下载
- 积分:1
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LED
说明: 一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
- 2019-06-28 15:18:09下载
- 积分:1
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234
在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下
变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所
采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字
下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了
数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)
- 2021-03-16 21:29:21下载
- 积分:1
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Verilog 编写的ISP1362的控制器IP核,altera公司DE2系统中的源程序
Verilog 编写的ISP1362的控制器IP核,altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
- 2022-07-27 16:33:17下载
- 积分:1
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1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES...
1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-08-08 19:22:01下载
- 积分:1
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数字滤波器
使用vhdl语言实现了数字滤波器,在Spartan-6上验证通过,最大支持240阶。源代码中滤波器为低通滤波器,可通过matlab中的fdatool工具生成滤波器系数,然后更改滤波器的通带和阻带。
- 2022-08-22 02:57:39下载
- 积分:1
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用fpga驱动lcd的原代码,是用vhdl语言实现的
用fpga驱动lcd的原代码,是用vhdl语言实现的-drive lcd by fpga,the source program is written by vhdl
- 2023-05-04 23:15:03下载
- 积分:1
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homework32
说明: 这是32位移位寄存器,是用verilog编写的,能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分:1