vhdl 数字时钟设计

说明：  使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

本文件是作为超大规模集成电路设计实验室课程（EC354）一部分进行的为期一学期的项目报告。我们的项目是一个4位8点FFT（快速傅立叶变换）核心的完全定制设计。实现的FFT类型是DIF（时间抽取）FFT。

完整的GMSK调制及维特比译码，程序中包括了高斯滤波器的设计，调制相位的计算，并采用了维特比译码算法解调出原始码元，最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)

基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

基于VHDL的数字频率计的设计.pdf 基于VHDL的频率计设计 很好用的 希望要用的同志来下载 (基于VHDL的频率计设计 很好用的 希望要用的同志来下载 )

这本书是夏宇文老师在几年前编写的，非常是和初学者，里面有哦对verilog 的详细讲解(a book write by xiyuwen ,This book provides a detailed explanation of verilog )