vhdl 数字时钟设计

任意维数矩阵求逆的fpga实现，矩阵求逆是矩阵运算中最重要且最难实现的一种运算(fpga implementaion of matrix inverse of any dimension)

uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code

基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.-Applicable to FPGA beginners, a procedure for light water, using the Verilog language.

使用Verilog HDL来控制机器人，六个高精密舵机，舵机运动非常流畅，舵机不抖动(FPGA to control the robot servo, six servos)

该代码实现了IIC对24C02的读写，写采用页写的方式，读采用随机的方式。(This code implements the IIC on 24C02 read and write, write, write using the page mode, read random way.)

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

FIFO的verilog描述(Verilog description of the FIFO)