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lcd
1602是目前最常用的显示器件,本例是通过verilog 代码实现1602的显示(1602 display)
- 2011-01-04 14:10:31下载
- 积分:1
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Combined unit GPS clock synchronization detection unit merger GPS synchronized c...
合并单元内GPS同步时钟的检测
合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
- 2023-05-04 14:30:04下载
- 积分:1
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McBSP
CPLD对mcbsp的收发操作,占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分:1
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通用:我新的FFT VHDL VHDL,我试图用Xilinx的FFT核,但当…
FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o
- 2022-06-20 20:06:05下载
- 积分:1
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A Dec example written in VHDL.
A Dec example written in VHDL.
- 2022-03-14 22:18:50下载
- 积分:1
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project_1
简单的一个Verilog小程序,适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分:1
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VHDLRS232Slave
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控
//制器,10个bit是1位起始位,8个数据位,1个结束
//位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实
//现相应的波特率。程序当前设定的div_par 的值是0x145,对应的波特率是
//9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
//划分为8个时隙以使通信同步.
//程序的工作过程是:串口处于全双工工作状态,按动key1,FPGA向PC发送“21 EDA"
//字符串(串口调试工具设成按ASCII码接受方式);PC可随时向FPGA发送0-F的十六进制
//数据,FPGA接受后显示在7段数码管上。
//视频教程适合我们21EDA电子的所有学习板(this is a base vhdl for uart progarm.)
- 2013-08-22 10:42:06下载
- 积分:1
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asynchronous-fifo
同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分:1
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uart
一个实用的uart协议模块,使用verilog 实现(A practical uart protocol modules, use verilog to achieve)
- 2013-07-25 11:43:34下载
- 积分:1
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一款介绍Soc使用的PDF文档供大家看和实践,还是有一定参考价值的!...
一款介绍Soc使用的PDF文档供大家看和实践,还是有一定参考价值的!-A description Soc using PDF documents for everyone to see and practice, there are still some reference value!
- 2022-01-25 23:50:29下载
- 积分:1