vhdl 数字时钟设计

NiosII_Exercises_Ver3,this niosII 3.o for cyclone

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

altera niosii SOPC helloword 学习-altera niosii SOPC helloword learning

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

Dynamic Power Management for the Iterative Decoding of Turbo Codes

0-99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦 -0-99 notation VHDL source, comprehensive guide book on the experiment can be used by everyone to download Oh

使用altera公司的FPGA进行VHDL开发，使用quartus2 9.0 软件在EP1C3T144C8开发板上实现跑马灯输出。-Altera company s FPGA using VHDL to the development, use quartus2 9.0 software EP1C3T144C8 Development Board to achieve ticker output.

this is the vhdl code for the arithmetic logic unit.enjoy!