vhdl 数字时钟设计

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

说明：  FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)

数字电子琴控制器的ＶＥＲＩＬＯＧ代码，含中文注释．-The number of organ controller Verilog code, with English Notes.

基于VHDL语言的CORDIC算法实现，用于计算sin(x),cos(x)等，实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)

卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve

用vhdl编写的主从式代码，会比较接近，它涉及i2c接口，主从式，每行都有注释，我建议如果你想对代码进行编辑就使用灵活的编辑器

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)

用可编程逻辑器件实现PWM波形即PWM波形发生器-Using programmable logic devices that realize PWM waveform PWM Waveform Generator

序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。