Mainly on the introduction MAGIC3000 series CPLD development board of the 10 exa...

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

VHDL programmes for basic digital circuits. begineers can learn easily

基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏！（可以使用RS2键盘进行控制）(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))

1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)

使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)

fft变换三个中的一个（站长：三个代码算一个）-fft transformation of a three (head : It is a code 3)

本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.