FPGA Verilog HDL模拟IIC通讯接口

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

自适应均衡器

说明：  FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new design

this is the vhdl code for the arithmetic logic unit.enjoy!

基于CS的一维距离像（HRRP）及FFT成像对比(CS-based HRRP and FFT HRRP)

Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)