FPGA Verilog HDL模拟IIC通讯接口

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

VHDL设计实体的基本结构 VHDL的语言要素 用VHDL实现电路设计的方法 VHDL设计流程-VHDL design entities, the basic structure of the language element of VHDL using VHDL circuit design approach to achieve VHDL design flow

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

本代码仿真了WCDMA小区搜索。cell_search_cpich scramble wcdmasource(This code emulation WCDMA cell search. cell_search_cpich scramble wcdmasource)

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!

Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

数字波形存储器VHDL源码，基于Quartus II开发。-Digital waveform memory VHDL source code, based on the Quartus II development.

VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！-VGA test procedure can be displayed color stripes, using VHDL language, tested and stable operation with Notes!