VHDL design entities, the basic structure of the language element of VHDL using...

说明：  matlab code for JTAG cable checking

zedboard的资料说明书，可以帮助你理解(zedboard data sheets, can help you understand)

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code

说明：  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)

cpld下在线资料ByteBlaster-CPLD under the online information ByteBlaster

简单介绍了直接数字频率合成技术(DD S)，利用DDS设计任意 波形发生器，其能够产生矩形波、正弦波、三角波、锯齿波等多种波形 -A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.

xilinx ise开发环境中fft IP核调用，仿真(Xilinx ise development environment FFT IP core call, simulation)

利用verilog实现对SD卡的控制，可以实现对SD卡的读写。(Verilog SD)

verilog延时电路的不同写法，和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)

fpga Verilog 控制读写flash (fpga Verilog flash )