数字波形存储器VHDL源码，基于Quartus II开发。

The description header can be found in signal_processing_library.h.

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

说明：  1、SignalTap II Logic Analyzer使用方法； 2、掌握捕获条件的设置 3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer; 2. Master the setting of capture conditions 3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码(H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code)

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

说明：  FSK VHDL FSK调制与解调VHDL程序及仿真(FSK VHDL )

4*4键盘设计，能运行，是我自己编译的，是初学者的工具(4* 4 keyboard design, can run my own compilation, is a tool for beginners)

VHDL控制VGA 在显示器上显示图形，分辨率800X600，晶振50Mhz-VGA control with VHDL

基于FPGA的出租车计价器，欢迎大死同学多多交流(FPGA-based Taximeter, welcomes the dead students more exchanges)