数字波形存储器VHDL源码，基于Quartus II开发。

FSK信号发生器，基于VHDL语言，好用的！-FSK signal generator, based on the VHDL language, useful!

基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)

基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

此代码包含非常有趣实现想法加密使用 vhdl 语言使用 Xilinx 的工具 ！希望你可以自定义和使用供您自己个人使用的这份工作 ！住宿已连接并且放松的感觉，要问的问题

基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

LED闪烁的VHDL代码