verilog实现的1024位的大数模逆算法，引入RAM作为数据通道

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240

基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

xilinx accel dsp实例项目工程-xilinx accel dsp project

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector

说明：  vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

or1200 PS2_Core code

用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM，代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)