verilog实现的1024位的大数模逆算法，引入RAM作为数据通道

说明：  汉明编码和解码的硬件描述语言（verilog），其被编解码的数据为M序列。 建议运行软件为Quartus.(failed to translate)

VHDL数字系统设计和工程实践1，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

对于学习FPGA的同学来说仿真是必不可少的流程 但是仿真的方法signal tap是必须掌握的(For students learning FPGA simulation is an essential process but the simulation method tap signal is a must)

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

     提供2个VHDL程序实现键盘显示的功能，第一个是16*16点阵显示“北京欢迎”，用VHDL语言编程实现，串烧在单片机实验工具箱上，让单片机点阵键盘上依次显示“北京欢迎”的字样。另附有LED数码管循环显示0～9数字的VHDL程序 ，成功串烧后，键盘上连续显示0~9这10个数字。

Basic VHDL code to create a sine wave generator for an FPGA board.

VHDL Coding style guide

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)

This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.