Radix-8 Booth Encoded Modulo

ADC Reference code!Clock 100kHz

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

LPDDR2 SDRAM memories compliant to JEDEC JESD209-2.

异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation

说明：  ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

verilog 语言实例，对于新手学习有很大帮助的实例-Examples of Verilog language, the novice has to learn very helpful examples of

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

在这里设计的是时分复用系统，就是要将三路8比特数据复用到同一信道上进行传输(Here is the design of time division multiplexing system, is to take the road three 8 bit data multiplexed onto the same channel for transmission)

vga 测试代码，可以显示任意彩条，棋盘，花纹(VGA test code, can display any color bar, chess board, decorative pattern )

利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)