Radix-8 Booth Encoded Modulo

this is a verilog code of true random number generator using butterfly puf

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

基于fpga和51单片机的等精度频率计，通过fpga对信号进行采集，数据传给单片机计算，再由12864进行显示，可进行频率，周期，脉宽，占空比，幅值等的测量。(Fpga and 51 microcontroller based precision frequency meter, through fpga for signal acquisition, data to the microcontroller to calculate, and then by 12864 for display, can be measured frequency, period, pulse width, duty cycle, the amplitude and the like.)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)

Configurable cpu core that supports Z80, 8080 and gameboy instruction sets

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

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