MCU and FPGA communication functions: SCM control FPGA to write a byte of data...

格子玻尔兹曼方法模拟poiseuille流，半反弹边界，适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)

Code VHDL for control VGA FPGA: Xilinx, Altera

DDS in our camera design

上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换-Shanghai Bund to see the largest LED display in the kernel source code, mainly to complete the long-distance video signal transmission codec conversion and interface

verilog编写的流水线模块-Verilog modules prepared by the Pipeline

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

说明：  ucos II 中文手册额，可以学习一下哦(UCOS II Chinese manual volume, you can learn it)

基于FPGA的VERILOG语言的DS18B20温度检测程序，代码自测可用(FPGA based VERILOG language DS18B20 temperature detection program, code self test available)

verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)

其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)