MCU and FPGA communication functions: SCM control FPGA to write a byte of data...

TI DSP XDS100V3仿真器原理图Rev2.0(TI DSP XDS100V3 schematic Rev2.0)

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)

（1）能够测试10HZ~10MHZ的方波信号； （2）电路输入的基准时钟为1HZ，要求测量值以8421BCD码形式输出； （3）系统有复位键； （4）采用分层次分模块的方法，用Verilog HDL进行设计，并对各个模块写出测试代码； （5）具体参照说明文档（包含源代码，仿真图，测试波形，详细的设计说明）(A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code; (3) the system has a reset key; (4) adopt the method of layering sub sub module and design with Verilog HDL; (5) write test simulation program.)

fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz

FFT with fix point 2*N

I2C总线在可编程逻辑器件上实现的VHDL源码-VHDL source codes for realizing I2C

code qui affiche une image sur ecran vga

cic设计 verilog verilog(cic verilog design verilog)

Rotary Encoder Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel. Events counter for the Rotary Encoder and displaying the events on the front panel Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).