Vending machine design, source code, in the hope that useful

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.

verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support

给予QPSK调制的OFDM例程，简单明了的表述了OFDM的通信原理(Given OFDM QPSK modulation routine, simple expressions of OFDM communication theory)

FPGA源代码公布，包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序，LED静态显示ADC0809 VHDL控制程序，DAC0832 接口电路程序

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs

24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。(24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.)

Program for simulate a prtsc