一个在Xilinx spartan3实现的时钟，具有时分秒的计时显示以及年月日的显示，很有参考价值

JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.

verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation

说明：  BUS documentation and map reffereces

用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)

数字时钟，可以实现(1) 显示日期功能（年、月、日、时、分、秒以及） (2) 可通过按键切换年、月、日及时、分、秒的显示状态 (3) 可随时调校年、月、日或时、分、秒 (4) 可每次增减一进行时间调节 (5) 可动态完整显示年份，实现真正的万年历显示 (6) 可显示温度 (Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)

ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99

这是使用systemgenerator的一个入门程序和范例使用matlab和system generator共同实现，并配有教学文档，清晰简单，易懂(This is an entry using systemgenerator procedures and examples using matlab and the system generator together to achieve, and with a teaching document, clear and simple and easy to understand)

使用飓风开发板，完成了100M，频率计设计，并可在数码管显示

本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)

sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)