主要是RS

verilog file , FPGA controll vga display- verilog file , FPGA controll vga display

这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting

基于FPGA的电子密码锁设计-已在开发板上成功运行，通过老师检验。(FPGA based electronic password lock design- has been successfully developed on the development board, through the teacher inspection.)

mux2to1.vhd二选一电路mux2_1.vhd二选一电路mux2_1.bdf二选一电路mux3to1.vhd三选择电路mux3to1_1.vhd三选一选一个电路mux4to1.vhd 4

51单片机的下载器PCB图，可以用于at89cXX和at89c0xx系列的单片机的程序烧录，简单好用！使用proteus画的板。(51 MCU PCB map downloader, can be used at89cXX and procedures for microcontroller series at89c0xx burning, easy to use! Drawing board with proteus.)

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

说明：  FPGA Verilog浮点数乘法运算，采用单精度浮点型小数格式，运算结果精度可设置，可封装成IP核(FPGA Verilog floating-point multi operation, using single precision floating-point decimal format, the accuracy of the operation results can be set, can be packaged into IP core)

mdct, it contains DOC,MATLAB,source,synthesis.

基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)

Traffic light program in c presents what happens in our daily life at traffic light signals.