主要是RS

通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

程序主要用硬件描述语言（VHDL）实现： 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。

Free 8051 core upload

对原信号进行拉格朗日插值运算，实现信号重采样(The original signal Lagrange interpolation operation, to achieve signal resampling)

VHDL-2008 Just the New Stuff Peter J. Ashenden Consultant Ashenden Designs

高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

说明：  DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)