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Frecuencymeter
Frecuencymeter digital, clk frequency 10 MHZ, exhibition in 7 segments
- 2009-09-17 02:49:40下载
- 积分:1
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1151175
Image Embedded VHDL Code by using watermarking technique
- 2013-03-14 16:53:07下载
- 积分:1
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四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D...
四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
- 2023-04-13 16:10:03下载
- 积分:1
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LED-clock-display
利用单片机控制LED时钟显示,以及闹钟,程序较大,但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分:1
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FPGA-basedhardwareimplementationofneuralnetworks
基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)
- 2009-04-15 05:44:09下载
- 积分:1
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regress-900055
The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.
- 2013-12-27 00:29:58下载
- 积分:1
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MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus
MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
- 2023-05-21 22:20:04下载
- 积分:1
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xilinx CTC IPcore(encoder 和 decoder)的标准测试,未经信道加噪
xilinx CTC IPcore(encoder 和 decoder)的标准测试,未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
- 2022-04-25 17:11:32下载
- 积分:1
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UDP
用verilog实现的UDP协议,包括arp,udp,ip分段协议等,对于想用FPGA实现TCP/IP协议的人来说,应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)
- 2021-04-05 04:39:03下载
- 积分:1
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";Verilog HDL设计指南";5
《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5
- 2022-04-21 22:39:14下载
- 积分:1