主要是RS

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

Multi-Digital Down Converter design.

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)

FPGA设计的四种常用思想与技巧分享:串并转换设计技巧、流水线设计思想……(FPGA design of four common ideas and techniques)

说明：  实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

说明：  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

it is a matrix library. it is needed for fir fier.

vhdl code for carry lookahead addder