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VHDL achieve a frequency measurement of dollars, development environment for any...
一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境
-VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
- 2022-01-28 17:39:53下载
- 积分:1
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crc16CCITT
自己用verilog编写的crc16-ccitt码的产生,是并行的。(Crc16-ccitt code written in verilog generate parallel.)
- 2012-12-13 09:46:58下载
- 积分:1
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bujinconrrol
步进电机定位控制系统,VHDL程序,里面有注释(Stepper motor position control system, VHDL program, there are comments)
- 2010-11-27 17:36:34下载
- 积分:1
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e_BIU
说明: isa MEMORY PLAN eu biu asm
- 2020-06-25 19:20:02下载
- 积分:1
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ModelsimPDFWordPPT
个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)
- 2009-09-20 11:37:19下载
- 积分:1
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webserver_c3
The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)
- 2014-03-23 20:00:14下载
- 积分:1
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uart_tr(3)
uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )
- 2015-06-08 21:02:17下载
- 积分:1
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用VHDL语言编写的写存储器程序,可下载在FPGA中使用
用VHDL语言编写的写存储器程序,可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
- 2022-06-17 11:46:31下载
- 积分:1
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基于VHDL数字频率计
基于vhdl可用的数字频率计,误差较小,精准度较高。文件中还包含了与arm的通信模块、
- 2022-03-05 17:19:11下载
- 积分:1
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clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分:1