基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出...

说明：  xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)

用FPGA实现OFDM系统，硬件语言为Verilog，环境为xilinx，详细介绍了接收机和发射机各个模块的源代码(OFDM system with a FPGA implementation, hardware language Verilog, environment xilinx, details of receiver and transmitter modules source code)

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

本科毕业设计，简易逻辑分析仪，重点在于用CPLD搭建显卡，输出VGA信号驱动显示器显示逻辑波形(A design for LA,use cpld to generate VGA signals.)

一个游戏程序vhdl源码，供大家参考，希望有兴趣的人下载-VHDL source code of a game program for your information, I hope those who are interested in downloading

万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )