登录
首页 » VHDL » 基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出...

基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出...

于 2023-03-31 发布 文件大小:3.19 kB
0 143
下载积分: 2 下载次数: 1

代码说明:

基于VHDL语言的并串转换程序,有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • DDC_matlab
    实现数字变下频的matlab程序,CIC,HB,FIR滤波器代码都在其中(Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it )
    2021-01-09 11:28:53下载
    积分:1
  • fpga clock design, the information is better, for your reference, non
    fpga clock 设计,资料较好,供大家参考,非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh
    2022-10-20 15:50:02下载
    积分:1
  • claa
    vhdl code for carry lookahead addder
    2014-02-05 00:26:26下载
    积分:1
  • sysgen_gs
    Xilinx system generator
    2020-12-25 15:39:04下载
    积分:1
  • Some useful things to know about picoblaze microcontroller.
    Some useful things to know about picoblaze microcontroller.
    2022-06-12 10:25:48下载
    积分:1
  • 倍频器
    倍频器-WE
    2022-08-16 20:57:43下载
    积分:1
  • exercise3
    用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
    2013-08-30 11:12:09下载
    积分:1
  • DUC
    说明:  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)
    2021-04-09 09:58:59下载
    积分:1
  • FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
    FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
    2022-09-14 14:30:09下载
    积分:1
  • 基于IIC的EEPROM模型代码
    说明:  基于IIC协议的EEPROM模型,可实现串行数据转并行数据,并行数据转串行数据,分为EEPROM模块,EEPROM_WR模块,signal模块,Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)
    2020-10-02 00:30:24下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载