基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出...

实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中(Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it )

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

vhdl code for carry lookahead addder

Xilinx system generator

Some useful things to know about picoblaze microcontroller.

倍频器-WE

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

说明：  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)

FPGA实现的LCD接口，VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera

说明：  基于IIC协议的EEPROM模型，可实现串行数据转并行数据，并行数据转串行数据，分为EEPROM模块，EEPROM_WR模块，signal模块，Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)