Documentation Of Digital Electronic Systems With VHDL from US DOD.

msk的verilog程序 利用ＦＰＧＡ实现-MSK procedures for the use of Verilog FPGA realize

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )

基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera

一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)

静态RAM是由MOS管组成的触发器电路，每个触发器可以存放1位信息。只要不掉电，所储存的信息就不会丢失。因此，静态RAM工作稳定，不要外加刷新新电路，使用方便。但一般SRAM的每一个触发器是由6个晶体管组成，SRAM芯片的集成度不会太高，目前较常用的有6116（2K×8位），6264（8K×8位）和62256（32K×8位）。6264RAM有8192个存储单元，每个单元为8位字长。-Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not brown-out, the stored information will not be lost. Therefore, the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of six transistors, SRAM chip integration will not be too high, there are currently more commonly used 6116 (2K × 8 bit), 6264 (8K × 8 bit) and 62256 (32K × 8 bits). 6264RAM have 8192 storage units, each for 8-bit word length.

VHDL参考例程--日如DAC0832接口电路程序-VHDL reference routines- on procedures such as the DAC0832 Interface Circuit

vendingmachine vhdl code

学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.

CORDIC(Coordinate Rotation Digital Computer)算法即坐标旋转数字计算方法。 CORDIC算法,能够通过平移和累加快速实现基础的数学函数,包括三角函数,开方,指数,对数,平方根等函数。(CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.)

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)