based on the nios ii drive the gpa module of altera de1 develop board,it s only...

manchester_verilog源代码(manchester_verilog source code)

quick reference guide to verilog HDL

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

测试人体视觉的反应时间，可以作为vhdl编程的练习之用，也可以更进一步的开发成为具有商业价值的产品，这里面只是能够实现测试人体视觉反应时间的基本功能的程序-Test of human visual reaction time, can be used as VHDL programming exercises used can also be further developed into products with commercial value, there is only able to realize the human visual reaction time test the basic functions of the procedures

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)

mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过 (mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

Frecuencymeter digital, clk frequency 10 MHZ, exhibition in 7 segments

Verilog经典教程，非常好的资料！值得一看！(Classic Verilog tutorials, very good information! Worth a visit!)