based on the nios ii drive the gpa module of altera de1 develop board,it s only...

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.

IEEE1588de FPGA 程序，已测试，可直接用，方便(IEEE1588de FPGA program has been tested, can be directly used to facilitate)

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

串口收发程序，成功通过仿真，可以用来学习(Serial transceiver,It is successful through simulation and can be used to learn)

four bit counter verlog source code for veriwell including test bench

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.

使用CycloneIV芯片，实现对高精度ADCad9226的数据采集。内有详细代码说明，并附有调试结果(Use CycloneIV, to achieve high-precision data acquisition ADCad9226. Along with debugging results)

the interface design of pcie based on FPGA