一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

本例为ADC0809接口电路VHDL程序原代码-The ADC0809 Interface Circuit Example for VHDL program source code

DEMO中完成WIAGAND26/32的（EMP7128实现）协议程序源代码-DEMO completed WIAGAND26/32 (EMP achieved) agreement procedure source code

manchester_verilog源代码(manchester_verilog source code)

说明：  实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

uvm apb verification env

基于vhdl的按键检测程序。可以有效消除抖动(vhdl key dectect program)