一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。(verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。)

基于单片机的DDS数字信号发生器设计，可以产生正弦波。三角波等(Design of DDS digital signal generator based on MCU, can produce sine wave. Triangular wave)

用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted

说明：  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)

VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)

基于FPGA的温度计源代码，VHLL语言-Thermometer-based FPGA source code, VHLL language