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111186763ddqpsk
说明: 这是一个关于OQPSK的Matlab程序
这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)
- 2010-04-21 12:41:59下载
- 积分:1
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Verilog_code_for_AWGN
说明: verilog实现awgn信道噪声的代码,支持可变的信噪比。利用移位寄存器来实现伪随机序列。(verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. )
- 2021-01-14 16:48:47下载
- 积分:1
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QuarusII91
这是QuarusII中文的用户指南!希望大家有用(This is a QuarusII Chinese User' s Guide! Hope that useful)
- 2010-01-09 21:50:10下载
- 积分:1
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nco11000
实现输入一正弦波和噪声的叠加,介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分:1
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oc8051 Verilog代码,关于
verilog code,about oc8051
- 2023-04-16 08:45:03下载
- 积分:1
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Verilog的150个经典设计实例
说明: Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)
- 2021-03-17 16:49:20下载
- 积分:1
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Altium Partner SN-1000010 r10
说明: Browser modularization processing, browser modularization combing, browser modularization expansion
- 2020-06-24 04:20:01下载
- 积分:1
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AXI-HP-PDMAPGIC
本文参考了Xilinx 官方文档UG873,“System Design Using Processing System High
Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。
本例中AXI CDMA 部分扮演主机,从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目
的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)
- 2014-12-23 10:27:24下载
- 积分:1
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DE2 115 BCD 3 位数计数器
在这个项目中我们使用 DE2 115 板上显示每次通过转移在左边按下某个键滚动你好。
这种架构使用管道和多路复用器
- 2022-01-26 08:10:34下载
- 积分:1
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Array-multiplier
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
- 2015-02-21 12:59:12下载
- 积分:1