test bench for alu 6 functions

codes for zynq devices

说明：  适合入门及进阶的100个VHDL练习题，从易到难(100 VHDL exercises for beginners and advanced students, from easy to difficult)

此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down

说明：  da的代码,在VHDL的编译环境下的开发。是一种集约的形式。(DA convert)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )