test bench for alu 6 functions

实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

说明：  对于有经验的用户和新用户写的，这本书给您的Verilog HDL的广泛报道。该书强调了实际设计和验证的角度，而不是只注重Verilog的语言方面。(Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. )

用于压缩感知 OMP 算法非常适合于压缩感知

2位并行加法器初学者必看初步了解FPGA-two count

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

说明：  iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现(iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation)

忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)

Multiplication in Verilog code

第一次输入和输出第一缓冲 vhdl 代码

自己写的FPGA实现电子琴的VHDL程序，曲目是两只老虎，用到一些模块，和片内存储间，呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)