test bench for alu 6 functions

利用8段数码管实现的秒表时钟，FPGA使用EP2C80208C8N，通过例化数码管控制模块、秒表计时模块、时钟进位模块等实现准确计时。

TIMING LEARNING -TIMING LEARNING

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)

说明：  串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)

实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用(it is good ...)

串口控制器，基于vivado软件下开发，包含代码及管脚分配文件(Serial port controller)

processor design istruction load pipeline ,hazard

HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.

VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only

1 前大灯可以随意打开和关闭； 2 当汽车左转弯的时候，前左转向灯闪烁，同时左后灯的3盏灯由右往左闪烁； 3 当汽车有转弯的时候，前右转向灯闪烁，同时右后灯的3盏灯有左往右闪烁； 4 当汽车减速或紧急刹车的时候，左后灯和右后等同时闪烁； 5 当汽车在左转弯的同时减速，则前左转向灯闪烁，左后灯的3盏灯由右往左闪烁，同时右后灯都点亮。 6 当汽车在左转弯的同时减速，则前右转向灯闪烁，右后灯的3盏灯有左往右闪烁，同时左后灯都点亮。 -a former headlamps can be opened and closed at will; 2 when the vehicle made a left turn when the former left to lights flickered. Left lights while the three lights flashing from right-go left; 3 when the vehicle is making a turn when a right turn to the former lights flickered. Right after the lights while the three lights are blinking right and left; 4 when the vehicle deceleration or when the emergency brake, Left and right after the lights blink, and so on; 5 when the vehicle made a left turn at the same time to slow down, and then to the left before the lights flickered. Left lights three lights flashing from right-go left, right after the lights are lit. 6 when a car made a left turn at the same time to slow down, and then right before the lights to flick