网站首页

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板...

于 2022-07-06 发布文件大小:1.91 MB

 0  168

下载积分: 2 下载次数: 1

我要下载

代码说明：

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

Writing Testbenches using System Verilog
Material to learn how to use system verilog and how to write testbenches for verification.

2018-02-09 17:24:25下载

积分：1
ethernet-verilog
非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)

2020-09-19 11:27:57下载

积分：1
imply logic
由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

2019-04-24 15:42:24下载

积分：1
各种常用模块的VHDL描叙实例，PDF格式
各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format

2022-03-21 06:08:45下载

积分：1
23565785scan_led
Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)

2006-12-11 17:11:41下载

积分：1
T144_PER_lcd1602
EP2C5T144 驱动 LCD1602液晶(LCD1602 LCD driver EP2C5T144)

2009-05-31 15:48:36下载

积分：1
all clock
说明：数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

2020-06-18 05:00:01下载

积分：1
基于CPLD的签到器的设计，用三维数组队人名进行储存
基于CPLD的签到器的设计，用三维数组队人名进行储存-Based on the attendance CPLD design, a few team names with three-dimensional storage

2023-01-07 09:45:04下载

积分：1
This an interpolating by 2 half
This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).

2022-03-06 22:11:21下载

积分：1
ofdm的verilog程序利用ＦＰＧＡ实现
ofdm的verilog程序利用ＦＰＧＡ实现-OFDM FPGA using the Verilog procedures realize

2022-08-07 01:11:15下载

积分：1

696516资源总数
106914会员总数
0今日下载

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板...

0 个回复

热门标签

热门下载